Concurrency theory - calculi and automata for modelling untimed and timed concurrent systems
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Language Preservation Problems in Parametric Timed Automata
Parametric timed automata (PTA) are a powerful formalism to model and reason about concurrent systems with some unknown timing delays. In this paper, we address the (untimed) languageand trace-preservation problems: given a reference parameter valuation, does there exist another parameter valuation with the same untimed language (or trace)? We show that these problems are undecidable both for g...
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In this thesis we develop a state space reduction technique for networks of timed automata based on unfoldings to alleviate the state space explosion problem due to concurrently enabled actions. For the purpose of verifying a system, standard model checking techniques construct its sequential state space that su ers an exponential growth when applied to distributed systems because of concurrent...
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Model checking is one of the most popular methods of automated verification of concurrent systems, e.g., hardware circuits, communication protocols, and distributed programs. Recently, the interest in automated verification is moving towards concurrent real-time systems. The properties to be verified are expressed in either a standard temporal logic like LTL and CTL, or in its timed version lik...
متن کاملForward and Backward Simulations Part I: Untimed Systems
A uni ed, comprehensive presentation of simulation techniques for veri cation of concurrent systems is given, in terms of a simple untimed automaton model. In particular, (1) re nements, (2) forward and backward simulations, (3) hybrid forward-backward and backward-forward simulations, and (4) history and prophecy relations are de ned. History and prophecy relations are abstract versions of the...
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We present a formalism for modular modelling of hybrid systems, the Cottbus Timed Automata. For the theoretical basis, we build on work about timed and hybrid automata. We use concepts from concurrency theory to model communication of separately defined modules, but we extend these concepts to be able to express explicitly readand write-access to signals and variables.
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